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Microprocessor
Headline News

Top Stories for February 5, 2002 (details below)
Ananova EU drops antitrust case against US chipmaker Intel Corp.
EE Times Latest Intel processor could steal the ISSCC show
Semiconductor Business News At ISSCC, Intel outlines McKinley 64-bit processor, but remains mum on 'Yamhill'
Semiconductor Business News At ISSCC, Intel to describe technology to enable 0.13-micron, 5-GHz processor
Neowin.net Intel to demo 5GHz non-cooled chip
Bloomberg.com Intel Says Memory Changes to Make New Server Chip Twice as Fast
EBN AMD's 300mm fab with UMC pivotal in race with Intel
Semiconductor Business News AMD/Motorola R&D deal will be phased out
Semiconductor Business News Via aims to become next $1 billion IC maker in Taiwan, preps 1-GHz processor
Asia BizTech VIA Technologies Marches Towards Reorganization
Truths...from the rumor mill
The Inquirer Apple could easily migrate to x86
The Inquirer AMD confirms first Hammer silicon out
The Inquirer Intel McKinley details leak
The Inquirer AMD extends CPUID space
The Inquirer Why did AMD choose UMC?

 

Microprocessor Headline News

Collected By Robert R. Collins

Week of February 3, 2002

Older News

February 5,, 2002

EU drops antitrust case against US chipmaker Intel Corp.

February 4, 2002
Ananova

European regulators have dropped an investigation into charges that Intel abused its dominant position to keep rivals from winning market share.

One of two complaints filed by Intel rivals with the European Commission has recently been withdrawn, commission spokeswoman Amelia Torres said.

After investigating the other complaint, the commission has "come to the preliminary conclusion that the accusations made against Intel are unfounded," she said. "Our intention is to close the file soon."

Latest Intel processor could steal the ISSCC show

By Stephan Ohr

February 4, 2002
EE Times

Intel Corp. will come to the International Solid-State Circuits Conference this week with tips for reining in runaway power as chip integration rises, following up on the call to arms it sounded at last year's ISSCC. Intel technology executives last week briefed analysts on techniques applied in the McKinley processor architecture as well as on such speculative technologies as body biasing and a new nonvolatile memory that could displace flash in cell phones and other space-constrained portables.

"Once a geek, always a geek," Pat Gelsinger, Intel's chief technology officer, joked as he described the topics Intel would broach at the conference.

At ISSCC, Intel outlines McKinley 64-bit processor, but remains mum on 'Yamhill'

By Mark LaPedus

February 4, 2002
Semiconductor Business News

During the International Solid-State Circuits Conference (ISSCC) here this week, Intel Corp. plans to outline more details about its McKinley line of 64-bit microprocessors, but it will remain mum about another new 64-bit technology, code-named "Yamhill."

At ISSCC, Intel plans to give six separate papers on McKinley, a 1-GHz, 64-bit processor line for use in high-end servers. The company plans to outline some new features of the processor, including an integrated, Level 3 cache design that promises to boost the overall speeds of the device, according to Intel executives at a press event in San Francisco last week. The event was intended to preview the company's activities at ISSCC, which will be held in San Francisco this week.

At ISSCC, Intel to describe technology to enable 0.13-micron, 5-GHz processor

By Mark LaPedus

February 4, 2002
Semiconductor Business News

During the International Solid-State Circuits Conference (ISSCC) here this week, Intel Corp. plans to provide more pieces of the puzzle that will enable the development of high-speed microprocessors, including a 0.13-micron, 5-GHz chip.

In various papers at ISSCC, Intel plans to describe three new, low-power "building blocks" to enable high-speed processors, including a 5-GHz integer execution core and an integrated 6.5-GHz arithmetic-logic unit (ALU) and scheduler. It will also describe a method to reduce the power consumption in chips by utilizing "forward and reverse body bias" technologies as well.

Intel to demo 5GHz non-cooled chip

February 5, 2002
Neowin.net

Chip Giant Intel has confirmed the large caches (3MB and above) it will include on future versions of the Itanium and has also further explained its tie in with Ovonics on these chips, first revealed here some months ago.

Intel is delivering eleven papers at the Solid State conference. Along with this, Intel has now formally released details of the 3MB cache on chip which it claims will deliver 1.5 to two times performance over the current designs. The low latency level three cache which will be included in the McKinley design is expected to give better performance for the processor, which will be used in servers.

Intel Says Memory Changes to Make New Server Chip Twice as Fast

By Dan Goodin

February 3, 2002
Bloomberg.com

Intel Corp.'s McKinley chip for computer servers will perform up to twice as fast as its predecessor, thanks to improvements that let it access larger chunks of memory more quickly and efficiently, the biggest maker of computer chips said.

McKinley is on track for release in the middle of the year and will offer 1 1/2 to 2 times the performance of Intel's current Itanium chip, said John Crawford, who directs the McKinley design team. Both chips digest data in larger, 64-bit chunks and are designed for high-end server computers, where Sun Microsystems Inc. dominates.

AMD's 300mm fab with UMC pivotal in race with Intel

By Jack Robertson

February 4, 2002
EBN

Advanced Micro Devices Inc.'s joint venture deal with UMC Corp. last week may prove to be the key to allowing the chip manufacturer to keep pace with rival Intel Corp.

By striking an alliance with UMC to build a 300mm-wafer fab in Singapore, AMD can now assure OEM and channel customers that it will be capable of producing enough processors in the coming years, said W.J. Sanders III, the company's chief executive in Sunnyvale, Calif.

AMD/Motorola R&D deal will be phased out

By J. Robert Lineback

February 1, 2002
Semiconductor Business News

While Advanced Micro Devices Inc. here and silicon foundry supplier United Microelectronics Corp. move into a major manufacturing alliance for PC processors and 300-mm wafer processing, the two companies are also faced with restructuring and merging their R&D activities to implement 65-nm processes for a planned joint-venture fab in Singapore by 2005.

The new partnership, announced on Thursday, signals the phase-out of an R&D alliance between AMD and Motorola Inc., which have been jointly developing copper-based CMOS processes for several years. That partnership will officially end after the 100-nm (0.10-micron) technology node, said Hector de J. Ruiz, president and chief operating officer of AMD.

AMD extends CPUID space

February 4, 2002
Neowin.net

There is a PDF up on the AMD site which a keen-eyed reader has spotted and we're not too sure what significance, if any, it has.

The 76 page PDF, called AMD Processor Recognition, and which you can find here, has a table on page 17 showing the CPU-ID functions in AMD chips.

But if you look closely this page says: "At any frequency above 1667 MHz, the model number should be omitted from the name string."

Via aims to become next $1 billion IC maker in Taiwan, preps 1-GHz processor

February 1, 2002
Semiconductor Business News

Via Technologies Inc. will shortly unveil a new corporate and product diversification strategy that could turn the company into the next $1 billion chip maker in Taiwan.

As part of its new and aggressive product strategy, Via is readying its first 1-GHz microprocessor and chip set line that supports the 333-MHz version of double-data-rate (DDR) synchronous DRAM standard. The company will offer two DDR333 chip sets, which will support processors from Advanced Micro Devices Inc. and Intel Corp.

VIA Technologies Marches Towards Reorganization

February 5, 2002
Asia BizTech

VIA Technologies Inc. President Chen Wen-chi announced a company reorganization that would hive off the branches of a business department, and keep only the global logistical e-business and financial division  as a common resource to be shared by all departments.

VIA enjoyed sales growth of 10 percent in 2001, but its profit margins slid by 4 percentage points and profits declined by 20 percent due to vicious price-slashing competition. Chen said the company will launch new product lines and transform itself into a completely new company in two years.

Truths...from the rumor mill

Apple could easily migrate to x86

By Mike Magee

February 1, 2002
The Inquirer

A READER HAS clarified how easy it would be for Apple to move to X86 and to other platforms, if that was its wish and will.

The core of MacOS X is extremely portable, he said, and as NeXTSTEP and OPENSTEP has run on SPARC, HP-PA/RISC, PowerPC, x86, and he said, perhaps the Alpha processor too.

This applies not just to the open source Darwin (BSD, Mach, device drivers) but also the entire object oriented framework of Cocoa, which he says, will run "on pretty much any CPU".

AMD confirms first Hammer silicon out

By Mike Magee

January 31, 2002
The Inquirer

AMD EXEC Ben Anixter presented some information about how his company is doing with its process technology this year and next, and said the firm has now successfully produced Hammer silicon.

AMD is pleased with the results, he claimed, with samples being supplied to its OEMs next quarter.

Speaking to the Banc of America, Anixter said that AMD will deliver .13 micron chips this quarter, by next quarter the crossover from the previous technology will be 50-50, and by the end of the year AMD will have completed the move, he claimed.

Intel McKinley details leak

By Mike Magee

January 31, 2002
The Inquirer

DETAILS OF A PRESENTATION by Intel to be made on February 4th are already available on its Web site, despite a notice on a presentation that says it's under embargo until the 4th February.

This is obviously some kind of SNAFU.

In the presentation, Intel reveals details of its next generation McKinley 64-bit processor, which as we noted in a report on the Solid State Conference the other day, will use low latency level three cache design.

AMD extends CPUID space

By Mike Magee

February 4, 2002
The Inquirer

THERE'S A PDF up on the AMD site which a keen-eyed reader has spotted and we're not too sure what significance, if any, it has.

The 76 page PDF, called AMD Processor Recognition, and which you can find here, has a table on page 17 showing the CPU-ID functions in AMD chips.

But if you look closely this page says: "At any frequency above 1667 MHz, the model number should be omitted from the name string."

Why did AMD choose UMC?

By Mike Magee

February 1, 2002
The Inquirer

THE £55,000 question on AMD's choice to build a 12-inch fab in 2005 is why UMC was chosen as its fab partner.

The two firms said yesterday that they will build the fab, in Singapore, with production starting in 2005.

Certainly, AMD recognises the economics of scale and it needs, quite fast, to get a 12-inch factory going. The equation is relatively simple - you get more processors from a big wafer than a small one.

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